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DLTS characterizations on GaN devices

ABG-102193 Emploi Junior
07/01/2022 CDD 8 Mois > 25 et < 35 K€ brut annuel
INSAVALOR - AMPERE
Villeurbanne - Auvergne-Rhône-Alpes - France
Electronique
  • Sciences de l’ingénieur
DLTS, characterization, GaN
15/02/2022
Recherche et Développement

Employeur

The candidate will be recruited by INSAVALOR, for AMPERE lab, UMR 5005.

Poste et missions

Work definition :
1. Training in using DLTS bench, bibliography of defects in GaN.
2. DLTS measurements on test structures (Schottky even transistor) and analyses.
3. DLTS measurements in SiC devices for comparison.
Analyses means the determination of deep levels and, if possible, to correlate the presence of these defects with other
features of the transistors.

Mobilité géographique :

Pas de déplacement

Télétravail :

Occasionnel

Prise de fonction :

15/03/2024

Profil

Project Engineer/ Ingénieur d’étude

General context : Ampere is focused on wide bandgap semiconductors for power applications and especially in GaN and SiC power devices. Although GaN devices are now commercially available, trapping characterization is a challenge, because the associated defects act on the dynamic on-resistance of the transistors. In this context, through the project nano2022/ICPEI, Ampere want to characterize trapping defects in GaN devices based on DLTS.
 

Objectifs

Objectives of the study : To characterize the materials by means of DLTS (Deep Level Transient Spectroscopy).
The DLTS bench at Ampere lab. allows measuring I-V, C-V and, of course, to achieve a transitory capacitance (or current) signals (CDLTS or I-DLTS) between ~20K and ~750K. And therefore, to detect deep levels in concentration about 10^ 6 times lower than the doping level.

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