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Hardware Implementation of Fully Pipelined Turbo Decoders

ABG-97990 Sujet de Thèse
04/05/2021 Financement public/privé
IMT Atlantique
Brest - Bretagne - France
Hardware Implementation of Fully Pipelined Turbo Decoders
  • Télécommunications
  • Informatique
  • Sciences de l’ingénieur
Hardware design, Channel Coding, Digital Communications

Description du sujet

Building on initial results on the hardware implementation of new decoding algorithms for Turbo decoding, the ANR funded JCJC project “TurboLEAP”, which is set to start 01.03.2021 and led by Stefan Weithoffer, will investigate the design of ultra-high throughput hardware architectures for the decoding of Turbo codes, focusing mainly on hardware design aspects. Within TurboLEAP, the PhD candidate is expected to play a significant role in the original approach applied traditionally by the members of the Mathematical and Electrical Engineering (MEE) department of IMT Atlantique consisting of a close interaction between Silicon and Algorithm design. Contrary to classical procedures, in this approach, algorithms are thought and derived from the start to consider at equal footing the hardware implementation and performance related constraints. Indeed, the candidate is expected to explore the full potential of fully pipelined iteration unrolled Turbo decoder hardware architectures. Throughputs of more than 1 Tb/s for large frame sizes with several thousands of information bits are targeted. Furthermore, decoder hardware architectures for Spatially coupled Turbo codes shall be investigated.

Prise de fonction :

01/09/2021

Nature du financement

Financement public/privé

Précisions sur le financement

Présentation établissement et labo d'accueil

IMT Atlantique

Under the supervision of well-established researchers in the field of Turbo coding/decoding and hardware
implementations, mainly Prof. Catherine Douillard and associate professors Charbel Abdel Nour and Stefan
Weithoffer, he will work in close collaboration with a PhD candidate planned to be recruited in the context algorithm design. Furthermore, a close collaboration with the Post-doctoral research fellow to be recruited for the TurboLEAP project and working both on the design of new Turbo codes and algorithms tailored for fully pipelined hardware architectures, is expected. Together, the assembled team shall achieve the required level of synergy between the simplified design of decoding algorithms and their impact on hardware implementations.

Profil du candidat

The candidate should hold a Master degree or an engineering degree in digital communications. The following
qualifications are beneficial for the completion of the project:

  • Experience with one or more of the following languages: C, C++, Python
  • Experience with one of the following hardware description languages: VHDL, Verilog, SystemC
  • Experience with hardware development on FPGA and/or ASIC
  • Advanced lectures on channel coding and communication systems
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