Design of a self-triggered architecture for an ultra-fast waveform digitizer

1.    Scientific context and motivation

In modern high energy physics experiments, the extremely precise measurement of particle time of arrival (with a resolution of the order of ten picoseconds) has become a crucial requirement to cope with high luminosity and event pile-up. The ultra-fast waveform digitization of the analogue signal has proved to be one of the most performant technique for time measurement, as illustrated by the SAMPIC family of integrated circuits.  
Recently, the SPIDER ASIC was developed for the LHCb experiment (at CERN LHC accelerator), based on a multi-bank waveform digitizer with high trigger rate capability. Like SAMPIC, it is self-triggered but optimized for quasi-synchronous signals with respect to LHC clock. However, for most non-collider applications, the circuits must be able to capture signals with random time. This suggests the idea of a new circuit, able to sample the input continuously like SAMPIC, equipped with a multi-bank system to optimize the dead time like SPIDER, and with self-triggered digitization like both ASICs.
This PhD thesis subject is involved in a Research and Technology project associating the LPCA (Clermont-Ferrand), IJCLab (Orsay) and CEA-IRFU (Saclay). The purpose is to design the next generation of fast waveform digitizers.

2.    Goals

The main goal is to modify the architecture of SPIDER, in CMOS 65nm technology, to make the sampling continuous and adapt the self-triggered digitization, while keeping excellent time resolution performance and low power.  The design work will be organised in 3 topics.

2.1    Modelling and system architecture

Before diving in transistor-level design, one must study the architecture must be studied and specify it using compact models for the elementary design cells. This will be crucial to optimize and verify the behaviour of the circuit under a high rate of random events. The student will model the whole architecture (sampling cells, trigger logic, digitization system, bank switching logic) using a behavioral description language (SystemVerilog). This step will allow to test and refine the architecture choices and check the functionality under different scenarios.

2.2    Design and optimisation of analogue and digital blocks

The input stage must be modified for continuous sampling. The addessing of switch capacitor cells (inherited from SPIDER) must be adapted to allow for continuous write and asynchronous trigger logic driving bank switching. This step will require analogue developments on switch capacitor array and bank management logic (RTL). 

2.3    Embedded digital pre-processing 

The digitization is affected by a systematic non-uniformity, which must be corrected in the processing flow. The focus of this 3rd topic is to explore the feasibility of an embedded correction, at least partial (pedestal subtraction) and to propose an implementation (including coefficient calibration from dedicated acquisitions).

The LPCA, Laboratoire de Physique de Clermont Auvergne, located on the “campus des Cézeaux” in Aubière near Clermont-Ferrand, is dedicated to Particle and Nuclei Physics, Cosmology and Theoretical Physics, and to applications in the fields of Health and Environment.

 The LPCA includes technical services and platforms for support and developments for the research projects held by the laboratory and its partners.

The thesis work will take place in the MiCA platform (Microélectronique Clermont Auvergne). The student will be supervised by a lecturer (MCF) and a research engineer.

You have a Master’s degree with a specialisation in micro-electronics / design and verification of integrated circuits. You have a solid culture in IC architecture and design (analogue and digital), and you master at least one HDL language.

You have a sense of investigation and method, curiosity, autonomy, and an ability to conduct a project towards achievement.