PD fellowship of the JSPS on the project :Smart Neuro-Interface for Home Autonomy: NEUROHOME

LIMMS/CNRS-IIS IRL 2820 (Laboratory for Integrated Micro Mechatronic Systems) is an international laboratory between the French CNRS (Centre National de la Recherche Scientifique) and Institute of Industrial Science (IIS), The University of Tokyo, located in Komaba, Tokyo. Since its creation in 1995, LIMMS has welcomed more than 380 researchers from France and Europe.

LIMMS opens a new postdoctoral position in the laboratory of Professor Kohno, Institute of Industrial Science, University of Tokyo, LIMMS/CNRS-IIS (IRL2820)
https://www.neumis.iis.u-tokyo.ac.jp

Responsibilities:

The principal investigator at Institute of Industrial Science (IIS), University of Tokyo, is working on novel neuromorphic circuits that consider detailed biophysical properties of neuronal cells. In contrast to the mainstream neuromorphic circuits that aim low-power execution of the artificial neural network tasks, the circuits in the lab aim reconstruction of the information processing in the brain microcircuits. We expect them to be a basis for a future brain-comparable artificial intelligence (AI) which is far more robust, flexible, and low-power than the current AI.

The project aims to demonstrate advantages of the lab’s biologically-detailed neuromorphic circuits in a practical engineering application. Specifically, we develop a complete, ultra-low power brain-computer interface (BCI) that enables intuitive and safe control of household appliances through Electroencephalogram (EEG)-based intention decoding. The system integrates stretchable EEG sensors, an ultra-low-noise analog front-end, and embedded spiking neural networks (SNN) for real-time classification and decision making. A secure command loop with confidence estimation and hardware interlocks ensures reliable appliance control. User studies will evaluate latency, power efficiency, robustness to motion, and usability in realistic home environments. NEUROHOME advances assistive neurotechnology by merging soft neurosensing with neuromorphic computing. It contributes to next-generation, human-centered robotics and inclusive innovation.

The lab has experience on developing biologically-detailed SNN models on a field-programmable gate array (FPGA) chip. It is well equipped with FPGA development boards and environment.

Fellowship periods and periods for arrival in Japan: Two years starting between September 1^st and November 30, 2026

Rewards: Paid equivalent to the JSPS Post-Doctoral position

1. Airfare: A round-trip air ticket (based on JSPS’s regulations)

2. Maintenance Allowance: 362,000 JPY per month

3. Miscellaneous: A setting-in allowance of 200,000 JPY, Overseas travel insurance, etc.

Skills:

Candidates are expected to have a background of spiking neuronal network modeling and FPGA programming. Skills on general electronic circuit design and knowledge on wet neuroscience especially on the morphology and physiology of neuronal cells will be helpful. They are expected to be ready to work on this interdisciplinary and cutting-edge research field.

Goals:

The recruited person should complete following three work packages (WPs).

WP1: Development of Acquisition and Stretchable Electronic Module. This module aims to acquire EEG signals from subjects and is composed of an analog front-end (AFE), analog-to-digital converter (ADC), and wireless signal transmission module (WST). The AFE should be equipped with a bandwidth filter and low-noise amplifier. The WST module should use the BlueTooth Low Engergy (BLE) for low-power consumption. This should be done within the first nine months.

WP2: Development of Embedded SNN Module (ESM). An SNN architecture for EEG-based intention decoding has to be developed utilizing the lab’s SNN-on-FPGA technolgy. It is expected to achieve a 90% accuracy with a low latency (less than 100 ms). This work package should be done before the end of the 18th month.

• WP3: Development of Decision Loop and Smart Applicance Control. This module produces and transmits the final control signal based on the output of ESM. Because ESM has maximum 10% error, safety guard system is required. For this purpose, a Secure Decision Protocol (SDP) has to be developed. Control output has to be validated through a confidence threshold combined with a confirmation mechanism such as a double gaze and a brief SSVEP pattern. Another core function of the module is control signal transmission by multiple communication devices including dry relays, infrared (IR) interface, and WiFi. The performance of the system has to be evaluated by multiple metrics including F1-score, false positive rate (FPR), time-to-action, power consumption, robustness to motion and perspiration. This should be done before the end of the project.